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general description the max3110e/max3111e combine a full-featured uni- versal asynchronous receiver/transmitter (uart) with ?5kv esd-protected rs-232 transceivers and inte- grated charge-pump capacitors into a single 28-pin package for use in space-, cost-, and power-con- strained applications. the max3110e/max3111e also feature an spi/qspi/microwire -compatible serial interface to save additional board space and microcon- troller (?) i/o pins. a proprietary low-dropout output stage enables the 2-driver/2-receiver interface to deliver true rs-232 per- formance down to v cc = +3v (+4.5v for max3110e) while consuming only 600?. the receivers remain active in a hardware/software-invoked shutdown, allow- ing external devices to be monitored while consuming only 10?. each device is guaranteed to operate at up to 230kbps while maintaining true eia/tia-232 output voltage levels. the max3110e/max3111e? uart includes a crystal oscillator and baud-rate generator with software-pro- grammable divider ratios for all common baud rates from 300baud to 230kbaud. the uart features an 8- word-deep receive fifo that minimizes processor over- head and provides a flexible interrupt with four maskable sources. two control lines (one input and one output) are included for hardware handshaking. the uart and rs-232 functions can be used together or independently since the two functions share only supply and ground connections (the max3110e/ max3111e are hardware- and software-compatible with the max3100 and max3222e). applications point-of-sale (pos) devices handy-terminals telecom/networking diagnostic ports industrial front-panel interfaces hand-held/battery-powered equipment benefits and features integration reduces cost and board space ? integrated rs-232 transceiver and uart in a single 28-pin package guaranteed 230kbps data rate spi/qspi/microwire-compatible c interface ? internal charge-pump capacitorsno external components required low-power operation reduces thermal dissipation ? true rs-232 operation down to v cc = +3v (max3111e) ? single-supply operation +5v (max3110e) +3.3v (max3111e) ? 600a supply current ? 10a shutdown supply current with receiver interrupt active hardware/software-compatible with max3100 and max3222e max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors 678 rs-232 db-9 cs sclk spi din dout p u a r t 9 12345 irq max3110e max3111e typical application circuit ordering information qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corp. ordering information continued at end of data sheet. pin configuration appears at end of data sheet. ? covered by u.s. patent numbers 4,636,930; 4,679,134; 4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and other patents pending. part max3110e cwi MAX3110ECNI 0? to +70? 0? to +70? temp. range pin- package 28 wide so 28 plastic dip v cc (v) 5 5 19-1494; rev 2; 2/15
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 2 www.maximintegrated.com absolute maximum ratings electrical characteristicsmax3110e (v cc = +4.5v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are measured for baud rate set to 9600baud at v cc = +5v, t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd (max3110e) ........................................-0.3v to +6v v cc to gnd (max3111e).........................................-0.3v to +4v v+ to gnd (note 1) ..................................................-0.3v to +7v v- to gnd (note 1) ...................................................+0.3v to -7v v+ to v- (note 1) ..................................................................+13v input voltages to gnd cs , x1, cts , rx, din, sclk .................. -0.3v to (v cc + 0.3v) t_in, shdn ...........................................................-0.3v to +6v r_in ..................................................................................?5v output voltage to gnd dout, rts , tx, x2 .................................-0.3v to (v cc + 0.3v) irq .......................................................................-0.3v to +6v t_out ...........................................................................?3.2v r_out .....................................................-0.3v to (v cc + 0.3v) tx, rts output current ....................................................100ma short-circuit duration x2, dout, irq (to v cc or gnd).............................continuous t_out (to gnd) .....................................................continuous continuous power dissipation (t a = +70?) 28-pin wide so (derate 12.5mw/? above +70?) ...........1w 28-pin plastic dip (derate 14.3mw/? above +70?) ....1.14w operating temperature ranges max311_ec_ _ .................................................. 0? to +70? max311_ee_ _ ................................................-40? to +85? storage temperature range ............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) pdip lead(pb)-free ........................................................+225? pdip containing lead(pb)..............................................+240? wide so lead(pb)-free..................................................+225? wide so containing lead(pb) .......................................+240? note 1: v+ and v- can have maximum magnitudes of 7v, but their absolute difference should not exceed 13v. shdni bit = 1 shdni bit = 0 2 input current i in1 25 ? v x1 = 0 or 5.5v parameter symbol min typ max units input low voltage v il1 0.2v cc v input high voltage v ih1 0.7v cc v v supply current with hardware and software shutdown i ccshdn(h+ s) 320 ? input capacitance c in1 5 pf input high voltage v ih2 0.7v cc v input low voltage v il2 0.3v cc v supply current i cc 0.6 2 ma supply current with hardware shutdown i ccshdn(h) 0.48 1 ma input hysteresis v hyst2 250 mv input leakage current i lkg1 ? ? input capacitance c in2 5 pf input high voltage v ih3 2.4 input low voltage v il3 0.8 v transmitter input hysteresis v hyst3 500 mv input leakage current i in3 ?.01 ? ? conditions shdn = gnd, shdni bit = 1 (note 4) v cc = 5v shdn = v cc , no load shdn = gnd (note 3) dc characteristics (v cc = +5v, t a = +25?) uart oscillator input (x1) uart logic inputs (din, sclk, cs, cts , rx ) ) rs-232 logic inputs (t_in, shdn ) )
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 3 www.maximintegrated.com ?5 electrical characteristicsmax3110e (continued) (v cc = +4.5v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are measured for baud rate set to 9600baud at v cc = +5v, t a = +25?.) (note 2) conditions units min typ max symbol parameter mv 500 v hyst4 input hysteresis v 0.8 v il4 input low voltage v 2.4 v ih4 input high voltage t a = +25? k 357 r in input resistance t a = +25?, v cc = 5v t a = +25?, v cc = 5v v -25 +25 input voltage range 0.9 i sink = 25ma; tx only output low voltage v ol2 0.4 v i sink = 4ma; dout, rts v cc - 0.5 i source = 10ma; tx only ? kv iec 1000-4-2 contact discharge ?5 iec 1000-4-2 air discharge sclk fall to dout valid t do 100 ns c load = 100pf cs to sclk hold time t csh 0 ns output low voltage v ol1 0.4 v output high voltage v oh1 v cc - 0.6 v ?.05 ?0 ? output voltage swing 5 5.4 v output resistance r o 300 10m output short-circuit current ?0 ma output leakage current i lkg2 ?5 ? esd protection ?5 output leakage current i lkg3 ? ? output high voltage v oh2 v cc - 0.5 v output capacitance c out1 5 pf output leakage current i lkg4 ? ? output low voltage v ol3 0.4 v output capacitance c out2 5 pf cs low to dout valid t dv 100 ns cs high to dout tri-state t tr 100 ns cs to sclk setup time t css 100 ns dout only, cs = v cc i sink = 1.6ma i source = 1ma 3k load on all transmitter outputs v cc = v+ = v- = 0, v out = ?v i source = 5ma; dout, rts v cc = 0 or 5.5v, v out = ?2v, transmitters disabled v irq = 5.5v i sink = 4ma human body model c load = 100pf c load = 100pf, r cs = 10k rs-232 receiver inputs (r_in) rs-232 esd protection (r_in, t_out) rs-232 receiver outputs (r_out) rs-232 transmitter outputs (t_out) uart outputs (dout, tx, rts ) uart irq outputs ( irq = open drain) uart ac timing
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 4 www.maximintegrated.com electrical characteristicsmax3110e (continued) (v cc = +4.5v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are measured for baud rate set to 9600baud at v cc = +5v, t a = +25?.) (note 2) conditions units min typ max symbol parameter ns 0 t dh din to sclk hold time ns 100 t ds din to sclk setup time ns 238 t cp sclk period ns 100 t cl sclk low time ns 100 t ch sclk high time ns 100 t cs0 sclk rising edge to cs falling tx, rts , dout; c l = 100pf ns 10 t r output rise time ns 200 t csw cs high pulse width ns 200 t cs1 cs rising edge to sclk rising edge tx, rts , dout, irq ; c l = 100pf ns 10 t f output fall time c l = 150pf to 2500pf 430 v/? receiver skew |t phl - t plh | 50 ns c l = 150pf to 1000pf transmitter skew |t phl - t plh | 100 ns t plh 150 ns transition-region slew rate 630 maximum data rate 250 kbps receiver propagation delay t phl 150 (note 5) c l = 150pf v cc = 5v, r l = 3k to 7k , t a = +25?, measured from +3v to -3v or -3v to +3v r l = 3k , c l = 1000pf, one transmitter switching receiver input to receiver output rs-232 ac timing
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 5 www.maximintegrated.com kv human body model shdn = gnd (note 3) shdn = v cc , no load shdn = gnd shdni bit = 1 (note 4) conditions pf 5 c in2 input capacitance ? ? i lkg1 input leakage current mv 165 v hyst2 input hysteresis ma 0.18 0.4 i ccshdn(h) supply current with hardware shutdown ma 0.45 1.4 i cc supply current v 0.3v cc v il2 input low voltage v 0.7v cc v ih2 input high voltage pf 5 c in1 ? 120 i ccshdn(h+ s) supply current with hardware and software shutdown v v 0.7v cc v ih1 input high voltage v 0.2v cc v il1 input low voltage units min typ max symbol parameter v x1 = 0 or 3.6v ? 25 i in1 input current 2 shdni bit = 0 shdni bit = 1 electrical characteristicsmax3111e (v cc = +3.0v to +3.6v, v a = t min to t max , unless otherwise noted. typical values are measured for baud rate set to 9600baud at v cc = +3.3v, t a = +25?.) (note 2) t a = +25?, v cc = 3.3v v cc = 3.3v mv 500 v hyst4 input hysteresis v 0.6 v il4 input low voltage v 2.4 v ih4 input high voltage ? ?.01 ? i in3 input leakage current mv 500 v hyst3 transmitter input hysteresis v 0.8 v il3 input low voltage v 2.0 v ih3 input high voltage t a = +25? k 357 r in input resistance t a = +25?, v cc = 3.3v v -25 +25 input voltage range ?5 esd protection iec 1000-4-2 air discharge ?5 iec 1000-4-2 contact discharge ? input capacitance dc characteristics (v cc = 3.3v, t a = +25?) uart oscillator input (x1) uart logic inputs (din, sclk, cs , rx ) ) rs-232 logic inputs (t_in, shdn) rs-232 receiver inputs (r_in) rs-232 esd protection (r_in, t_out)
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 6 www.maximintegrated.com electrical characteristicsmax3111e (continued) (v cc = +3.0v to +3.6v, v a = t min to t max , unless otherwise noted. typical values are measured for baud rate set to 9600baud at v cc = +3.3v, t a = +25?.) (note 2) output fall time t f 10 ns tx, rts , dout, irq ; c load = 100pf cs rising edge to sclk rising edge t cs1 200 ns cs high pulse width t csw 200 ns output rise time t r 10 ns tx, rts , dout; c load = 100pf sclk rising edge to cs falling t cs0 100 ns sclk high time t ch 100 ns sclk low time t cl 100 ns sclk period t cp 238 ns sclk fall to dout valid t do 100 ns din to sclk setup time t ds 100 ns din to sclk hold time t dh 0 ns c load = 100pf cs to sclk hold time t csh 0 ns cs low to dout valid t dv 100 ns cs high to dout tri-state t tr 100 ns cs to sclk setup time t css 100 ns c load = 100pf c load = 100pf, r cs = 10k 0.9 i sink = 25ma, tx only output low voltage v ol2 0.4 v ?5 v cc - 0.5 i sink = 4ma; dout, rts output low voltage v ol1 0.4 v output high voltage v oh1 v cc - 0.6 v output voltage swing ? ?.4 v output resistance r o 300 10m output short-circuit current ?0 ma output leakage current i lkg2 ? i source = 10ma, tx only parameter symbol min typ max units output leakage current i lkg3 ? ? output high voltage v oh2 v cc - 0.5 v output capacitance c out1 5 pf output leakage current i lkg4 ? ? output low voltage v ol3 0.4 v output capacitance c out2 5 pf dout only; cs = v cc i sink = 1.6ma i source = 1ma 3k load on all transmitter outputs v cc = v+ = v- = 0, v out = ?v i source = 5ma; dout, rts v cc = 0 or 3.6v, v out = ?2v, transmitters disabled v irq = 3.6v i sink = 4ma condition rs-232 receiver outputs (r_out) rs-232 transmitter outputs (t_out) uart outputs (dout, tx, rts ) uart irq output ( irq = open drain) uart ac timing
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 7 www.maximintegrated.com ns electrical characteristicsmax3111e (continued) (v cc = +3.0v to +3.6v, v a = t min to t max , unless otherwise noted. typical values are measured for baud rate set to 9600baud at v cc = +3.3v, t a = +25?.) (note 2) note 2: all currents into the device are positive; all currents out of the device are negative. all voltages are referred to device ground unless otherwise noted. note 3: i ccshdn(h) represents a hardware-only shutdown. in hardware shutdown, the uart is in normal operation and the charge pumps for the rs-232 transmitters are shut down. note 4: i ccshdn(h+s) represents a simultaneous software and hardware shutdown in which the uart and charge pumps are shut down. note 5: transmitter skew is measured at the transmitter zero cross points. receiver input to receiver output r l = 3k , c l = 1000pf, one-transmitter switching v cc = 3.3v, r l = 3k to 7k , t a = +25?, measured from +3v to -3v or -3v to +3v c l = 150pf (note 5) 150 t phl receiver propagation delay kbps 250 maximum data rate v/? 630 transition-region slew rate ns 150 t plh c l = 150pf to 1000pf ns 200 |t phl - t plh | transmitter skew ns 100 |t phl - t plh | receiver skew 430 c l = 150pf to 2500pf conditions units min typ max symbol parameter rs-232 ac timing
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 8 www.maximintegrated.com 0 10 5 15 30 35 40 25 20 50 0 1000 2000 250kbps 3000 4000 5000 rs-232 transceiver supply current vs. load capacitance max3110e/toc09 load capacitance (pf) supply current (ma) 45 transmitter 1 at data rate transmitter 2 at data rate 3k + c l 16 120kbps 20kbps 0 4 2 6 12 14 10 8 16 0 1000 2000 3000 4000 5000 rs-232 transmitter slew rate vs. load capacitance max3110e/toc11 load capacitance (pf) slew rate (v/ s) transmitter 1 at 250kbps 3k + c l -slew +slew -10.0 -5.0 -7.5 -2.5 5.0 7.5 2.5 0 10.0 0 1000 2000 3000 4000 5000 rs-232 transmitter output voltage vs. load capacitance max3110e/toc07 load capacitance (pf) transmitter output voltage (v) transmitter 1 at 250kbps transmitter 2 at 15.6kbps 3k + c l v out- v out+ typical operating characteristics (t a = +25?, unless otherwise noted.) 1000 900 0 -40 -20 40 60 100 uart supply current vs. temperature 200 100 800 700 max3110e-01 temperature ( c) supply current ( a) 020 80 600 500 400 300 max3110e, v cc = +5v max3111e, v cc = +3.3v 1.8432mhz crystal transmitting at 115.2kbps 10 9 0 -40 -20 40 60 100 uart shutdown current vs. temperature 2 1 8 7 max3110e-02 temperature ( c) shutdown current ( a) 020 80 6 5 4 3 1.8432mhz crystal max3110e, v cc = +5v max3111e, v cc = +3.3v 400 50 100 10k 1000 100k 1m uart supply current vs. baud rate 150 100 max3110e-03 baud rate (bps) supply current ( a) 200 250 350 300 1.8432mhz crystal max3110e max3111e +5v standby +5v transmitting +3v transmitting +3v standby 700 600 0 01 3 4 5 uart supply current vs. external clock frequency 100 500 max3110e-04 external clock frequency (mhz) supply current ( a) 2 400 300 200 max3110e v cc = +5v max3111e v cc = +3.3v 70 0 0 0.2 0.1 0.6 0.7 0.8 1.0 max3111e tx, rts, dout output current vs. output low voltage (v cc = +3.3v) 10 max3110e-05 voltage (v) output sink current (ma) 0.3 0.5 0.4 0.9 60 50 40 30 20 rts tx dout 90 80 0 00.2 0.1 0.6 0.7 0.8 1.0 max3110e tx, rts, dout output current vs. output low voltage (v cc = +5v) 10 70 max3110e-06 voltage (v) output sink current (ma) 0.3 0.5 0.4 0.9 60 50 40 30 20 rts tx dout
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 9 www.maximintegrated.com pin description positive terminal of internal inverting charge-pump capacitor. do not make any connection to this terminal. c2+ 24 negative terminal of internal inverting charge-pump capacitor. do not make any connection to this terminal. c2- 25 -5.5v generated by the internal charge pump. do not make any connection to this terminal. v- 26 ground gnd 27 rs-232 transmitter output 2 t2out 28 uart active-low interrupt output. open-drain interrupt output to microprocessor. irq 19 hardware shutdown input. drive shdn low to shut down the rs-232 transmitters and charge pump. drive high for normal operation. shdn 20 +5.5v generated by the internal charge pump. do not make any connection to this terminal. v+ 21 positive terminal of the internal voltage-doubler charge-pump capacitor. do not make any connection to this terminal. c1+ 22 negative terminal of the internal voltage-doubler charge-pump capacitor. do not make any connection to this terminal. c1- 23 spi/microwire serial-data input. schmitt-trigger input. din 15 spi/microwire serial-data output. high impedance when cs is high. dout 16 spi/microwire serial-clock input. schmitt-trigger input. sclk 17 uart active-low chip-select input. dout goes high impedance when cs is high. irq , tx, and rts are always active. schmitt-trigger input. cs 18 uart asynchronous serial-data (transmitter) output tx 14 uart crystal connection. leave x2 unconnected when using an external cmos clock. see the crystals, oscillators, and ceramic resonators section. x2 9 uart crystal connection. x1 also serves as an external cmos clock input. see the crystals, oscillators, and ceramic resonators section. x1 10 uart clear-to-send active-low input. read via the cts bit. cts 11 uart request-to-send active-low output. controlled by the rts bit. also used to control the driver enable in rs-485 networks. rts 12 uart asynchronous serial-data (receiver) input. the serial information received from the rs-232 receiver. a transition on rx while in shutdown generates an interrupt (table 1). rx 13 rs-232 receiver output 1, ttl/cmos r1out 5 rs-232 receiver input 1 r1in 6 rs-232 transmitter output 1 t1out 7 positive supply voltage v cc 8 rs-232 transmitter lnput 1, ttl/cmos t1in 4 rs-232 transmitter lnput 2, ttl/cmos t2in 3 pin rs-232 receiver output 2, ttl/cmos r2out 2 rs-232 receiver input 2 r2in 1 function name
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 10 www.maximintegrated.com detailed description the max3110e/max3111e contain an spi/qspi/microwire- compatible uart and an rs-232 transceiver with two drivers and two receivers. the uart is compatible with spi and qspi for cpol = 0 and cpha = 0. the uart supports data rates up to 230kbaud for standard uart bit streams as well as irda and includes an 8-word receive fifo. also included is a 9-bit-address recogni- tion interrupt. the rs-232 transceiver has electrostatic discharge (esd) protection on the transmitter outputs and the receiver inputs. the internal charge-pump capacitors minimize the number of external components required. the rs-232 transceivers meet eia/tia-232 specifica- tions for v cc down to the minimum supply voltage and are guaranteed to operate for data rates up to 250kbps. the uart and rs-232 functions operate as one device or independently since the two functions share only supply and ground connections. uart the universal asynchronous receiver transmitter (uart) interfaces the spi/ qspi/ microwire-compati- ble synchronous serial data from a microprocessor (?) to asynchronous, serial-data communication ports (rs- 232, irda). figure 1 shows the max3110e/max3111e functional diagram. included in the uart function is an spi/ qspi/ microwire interface, a baud-rate generator, and an interrupt generator. spi interface interrupt logic pr rx shift register pt tx shift register t2out t2in 9 pr rx buffer pt tx buffer pr rx fifo 9 9 9 9 9 9 4 internal 5k 5k internal internal internal t1out r2in t1in r2out r1in v+ gnd v- shdn irq r1out c1+ c1- c2+ c2- v cc rx x2 x1 tx cts rts baud-rate generator dout sclk cs din i/o charge pump max3110e/max3111e figure 1. max3110e/max3111e functional diagram
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 11 www.maximintegrated.com spi interface the max3110e/max3111e are compatible with spi, qspi (cpol = 0, cpha = 0), and microwire serial- interface standards (figure 2). the max3110e/ max3111e have a unique full-duplex-only architecture that expects a 16-bit word for din and simultaneously produces a 16-bit word for dout regardless of which read/write register is used. the din stream is moni- tored for its first two bits to tell the uart the type of data transfer being executed (see the write configuration register , read configuration register , write data register , and read data registe r sections). din (mosi) is latched on sclk? rising edge. dout (miso) should be read into the ? on sclk? rising edge. the first bit (bit 15) of dout transitions on cs ? falling edge, and bits 14? transition on sclk? falling edge. figure 3 shows the detailed serial timing specifi- cations for the synchronous spi port. only 16-bit words are expected. if cs goes high in the middle of a transmission (any time before the 16th bit), the sequence is aborted (i.e., data does not get written to individual registers). most operations, such as the clearing of internal registers, are executed only on cs ? rising edge. every time cs goes low, a new 16-bit stream is expected. an example of using the write configuration register is shown in figure 4. table 1 describes the bits located in the write config- uration, read configuration, write data, and read data registers. this table also describes whether the bit is a read or a write bit and the power-on reset state (por) of the bits. figure 5 shows an example of parity and word-length control. cs sclk sclk sclk sclk (cpol = 0, cpha = 0) (cpol = 0, cpha = 1) (cpol = 1, cpha = 0) (cpol = 1, cpha = 1) compatible with max3110e/max3111e not compatible with max3110e/max3111e din msb 13 14 12 11 10 9 8 7 6 5 4 3 2 1 lsb dout msb 13 14 12 11 10 9 8 7 6 5 4 3 2 1 lsb figure 2. compatible cpol and cpha timing modes ? ? ? ? ? ? ? ? ? ? ? ? cs sclk din dout t cso t css t cl t ds t dh t dv t ch t do t tr t csh t cs1 figure 3. detailed serial timing specifications for the synchronous spi port
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 12 www.maximintegrated.com 15 cs sclk din dout 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data updated 1 1 fen shdn tm rm pm ram ir st pe l b3 b2 b1 b0 rt 0 0 0 00 00 00 00 000 figure 4. write configuration register example idle second stop bit is omitted if st = 0. pe = 1, l = 1 time d0 start d1 d2 d3 d4 d5 d6 pt stop stop idle idle pe = 1, l = 0 d0 start d1 d2 d3 d4 d5 d6 d7 pt stop stop idle idle pe = 0, l = 1 d0 start d1 d2 d3 d4 d5 d6 stop stop idle idle pe = 0, l = 0 d0 start d1 d2 d3 d4 d5 d6 d7 stop stop idle figure 5. parity and word-length control
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 13 www.maximintegrated.com table 1. bit descriptions 0 pe por state write parity-enable bit. appends the pt bit to the transmitted data when pe = 1, and sends the pt bit as written. no parity bit is transmitted when pe = 0. with pe = 1, an extra bit is expected to be received. this data is put into the pr register. pr = 0 when pe = 0. the max3110e/max3111e do not calculate parity. 0 pe read reads the value of the parity-enable bit. 0 pm write mask for pr bit. irq is asserted if pm = 1 and pr = 1 (table 7). description 0000 0000 x pr read receive-parity bit. this bit is the extra bit received if pe = 1. therefore, pe = 1 results in 9-bit transmissions (l = 0). if pe = 0, then pr is set to 0. pr is stored in the fifo with the receive data (see the 9-bit networks section). 0 0 ir read reads the value of the ir bit. l bit type write b0?3 write baud-rate divisor select bits. sets the baud clock? value (table 6). b0?3 read baud-rate divisor select bits. reads the 4-bit baud clock value assigned to these registers. bit name bit to set the word length of the transmitted or received data. l = 0 results in 8-bit words (9-bit words if pe = 1) (see figure 5). l = 1 results in 7-bit words (8-bit words if pe = 1). 0 x l read reads the value of the l bit. pt write transmit-parity bit. this bit is treated as an extra bit that is transmitted if pe = 1. in 9-bit net- works, the max3110e/max3111e do not calculate parity. if pe = 0, then this bit (pt) is ignored in transmit mode (see the 9-bit networks section). 00000000 0 d0r?7r read eight data bits read from the receive fifo or the receive-buffer register. when l = 1, d7r is always 0. fen write fifo enable. enables the receive fifo when fen = 0. when fen = 1, fifo is disabled. 0 0 fen read fifo-enable readback. fen ? state is read. ir write enables the irda timing mode when ir = 1. no change xxxxxxxx cts read clear-to-send-input. records the state of the cts pin (cts bit = 0 implies cts pin = logic high). d0t?7t write transmit-buffer register. eight data bits written into the transmit-buffer register. d7t is ignored when l = 1. 0 pm read reads the value of the pm bit (table 7). 0 r read receive bit or fifo not empty flag. r = 1 means new data is available to be read or is being read from the receive register or fifo. if performing a read data or write data operation, the r bit will clear on the falling edge of sclk's 16th pulse if no new data is available. 0 rm write mask for r bit. irq is asserted if rm = 1 and r = 1 (table 7). 0 rm read reads the value of the rm bit (table 7). 0 ram write mask for ra/fe bit. irq is asserted if ram = 1 and ra/fe = 1 (table 7). 0 ram read reads the value of the ram bit (table 7). 0 rts write request-to-send bit. controls the state of the rts output. this bit is reset on power-up (rts bit = 0 sets the rts pin = logic high).
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 14 www.maximintegrated.com notice to high-level programmers: the uart follows the spi convention of providing a bidirectional data path for writes and reads. whenever the data is written, data is also read back. this speeds operation over the spi bus, and the uart needs this speed advantage when operating at high baud rates. in most high-level lan- guages, such as c, there are commands for writing and reading stream i/o devices such as the console or serial port. in c specifically, there is a ?utchar?command that transmits a character and a ?etchar?command that receives a character. if programmers were to write direct write and read commands in c with no underlying driver code, they would notice that a putchar com- mand is really a putgetchar command. these c commands assume some form of bios-level support for these commands. the proper way to implement these commands is to write driver code, usually in the form of an assembly-language interrupt-service routine and a callable routine used by high-level routines. this driver handles the interrupts and manages the receive and transmit buffers for the max3110e/max3111e. when a putchar executes, this driver is called and it safely buffers any characters received when the current character is transmitted. when a getchar executes, it checks its own receive buffer before getting data from the uart. see the c-language outline for a max3110e/ max3111e software driver in listing 1, which appears at the end of this data sheet. listing 1 is a c-language outline of an interrupt-driven software driver that interfaces to a max3110e/ max3111e, providing an intermediate layer between the bit-manipulation subroutine and the familiar putchar/getchar subroutines. the user must supply code for managing the transmit and receive queues as well as the low-level hardware interface itself. the interrupt control hardware must be initialized before this driver is called. table 1. bit descriptions (continued) por state description bit type bit name 0 shdni write software-shutdown bit. enter software shutdown with a write configuration where shdni = 1. software shutdown takes effect after cs goes high, and causes the oscillator to stop as soon as the transmitter becomes idle. software shutdown also clears r, t, ra/fe, d0r?7r, d0t?7t, pr, pt, and all data in the receive fifo. rts and cts can be read and updated while in shutdown. exit software shutdown with a write configuration where shdni = 0. the oscillator restarts typically within 50ms of cs going high. rts and cts are unaffected. refer to the pin description for hardware shutdown ( shdn input). 0 shdno read shutdown read-back bit. the read configuration register outputs shdno = 1 when the uart is in shutdown. note that this bit is not sent until the current byte in the transmitter is sent (t = 1). this tells the processor when it may shut down the rs-485/rs-422 driver. this bit is also set immediately when the device is shut down through the shdn pin. 0 ra/fe read receiver-activity/framing-error bit. in shutdown mode, this is the ra bit. in normal operation, this is the fe bit. in shutdown mode, a transition on rx sets ra = 1. in normal mode, a fram- ing error sets fe = 1. a framing error occurs if a zero is received when the first stop bit is expected. fe is set when a framing error occurs, and cleared upon receipt of the next prop- erly framed character independent of the fifo being enabled. when the device wakes up, it is likely that a framing error will occur. this error is cleared with a write configuration. the fe bit is not cleared on a read data operation. when an fe is encountered, the uart resets itself to the state where it is looking for a start bit. 0 st write transmit-stop bit. one stop bit will be transmitted when st = 0. two stop bits will be transmit- ted when st = 1. the receiver only requires one stop bit. 0 st read reads the value of the st bit. 0 tm write mask for t bit. irq is asserted if tm = 1 and t = 1 (table 7). 0 tm read reads the value of the tm bit (table 7). 1 t read transmit-buffer-empty flag. t = 1 means that the transmit buffer is empty and ready to accept another data word. 0 te write transmit-enable bit. if te = 1, then only the rts pin is updated on cs ? rising edge. the con- tents of rts , pt, and d0t?7t transmit on cs ? rising edge when te = 0.
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 15 www.maximintegrated.com write configuration register (d15, d14 = 1, 1) configure the uart by writing a 16-bit word to the write configuration register, which programs the baud rate, data word length, parity enable, and enable of the 8- word receive fifo. in this mode, bits 15 and 14 of the din configuration word are both required to be 1 in order to enable the write configuration mode. bits 13? of the din configuration word set the configuration of the uart. table 2 shows the bit assignment for the write configuration register. the write configuration reg- ister allows selection between normal uart timing and irda timing, provides shutdown control, and contains four interrupt mask bits. using the write configuration register clears the receive fifo and the r, t, ra/fe, d0r?7r, d0t?7t, pr, and pt registers. rts and cts remain unchanged. the new configuration is valid on cs ? rising edge if the transmit buffer is empty (t = 1) and transmission is over. if the latest transmission has not been completed (t = 0), the registers are updated when the transmission is over. the write configuration register bits ( fen , shdni, ir, st, pe, l, b3?0) take effect after the current transmis- sion is over. the mask bits ( tm , rm , pm , ram ) take effect immediately after sclk? 16th rising edge. bits 15 and 14 of the dout write configuration (r and t) are sent out of the max3110e/max3111e along with 14 trailing zeros. the use of the r and t bits is optional, but ignore the 14 trailing zeros. warning! the uart requires stable crystal oscillator operation before configuration (typically ~25ms after power-up). upon power-up, compare the write configu- ration bits with the read configuration bits in a software loop until both match. this ensures that the oscillator is stable and that the uart is configured correctly. read configuration register (d15, d14 = 0, 1) the read configuration register is used to read back the last configuration written to the uart. in this register, bits 15 and 14 of the din configuration word are required to be 0 and 1, respectively, to enable the read configuration mode. bits 13? of the din word should be zeros, and bit 0 is the test bit to put the uart in test mode (see the test mode section). table 3 shows the bit assignment for the read configuration register. test mode the device enters a test mode if bit 0 of the din config- uration word equals one when doing a read configura- tion. in this mode, if cs = 0, the rts pin transmits a clock that is 16-times the baud rate. the tx pin is low as long as cs remains low while in test mode. table 3 shows the bit assignment for the read configuration register. write data register (d15, d14 = 1, 0) use the write data register for transmitting to the tx- buffer and receiving from the rx buffer (and rx fifo when enabled). when using this register, the din and dout write data words are used simultaneously, and bits 13?1 for both the din and dout write data words are meaningless zeros. the din write data word con- tains the data that is being transmitted, and the dout write data word contains the data that is being received from the rx fifo. table 4 shows the bit assignment for the write data mode. to change the rts pin? output state without transmitting data, set the te bit high. if performing a write data operation, the r bit will clear on the falling edge of sclk? 16th clock pulse if no new data is available. read data register (d15, d14 = 0, 0) use the read data register for receiving data from the rx fifo. when using this register, bits 15 and 14 of din are both required to be 0. bits 13? of the din read-data word should be zeros. table 5 shows the bit assignments for the read data mode. reading data clears the r bit and interrupt irq . if performing a read data operation, the r bit will clear on the falling edge of sclks 16th clock pulse if no new data is available.
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 16 www.maximintegrated.com 6 st 0 7 ir 0 2 b2 0 3 b3 0 0 b0 0 1 b1 0 4 l 0 5 pe 0 10 rm 0 11 tm 0 8 ram 0 9 pm 0 12 shdni 0 13 fen 0 15 14 1 t din 1 dout r bit table 2. write configuration (d15, d14 = 1, 1) notes: bit 15: dout r = 1, data is available to be read or is being read from the receive register or fifo. r = 0, receive register and fifo are empty. bit 14: dout t = 1, transmit buffer is empty. t = 0, transmit buffer is full. bits 13?: dout zeros bits 15, 14: din 1,1 = write configuration bit 13: din fen = 0, fifo is enabled. fen = 1, fifo is disabled. bit 12: din shdni = 1, enter software shutdown. shdni = 0, exit software shutdown. bit 11: din tm = 1, transmit buffer empty interrupt is enabled. tm = 0, transmit buffer empty interrupt is disabled. bit 10: din rm = 1, data available in the receive register or fifo interrupt is enabled. rm = 0, data available in the receive register or fifo interrupt is disabled. bit 9: din pm = 1, parity bit high received interrupt is enabled. pm = 0, parity bit received interrupt is disabled. bit 8: din ram = 1, receiver-activity (shutdown mode)/framing-error (normal operation) interrupt is enabled. ram = 0, receiver-activity (shutdown mode)/framing-error (normal operation) interrupt is disabled. bit 7: din ir = 1, irda mode is enabled. ir = 0, irda mode is disabled. bit 6: din st = 1, transmit two stop-bits. st = 0, transmit one stop-bit. bit 5: din pe = 1, parity is enabled for both transmit (state of pt) and receive. pe = 0, parity is disabled for both transmit and receive. bit 4: din l = 1, 7-bit words (8-bit words if pe = 1) l = 0, 8-bit words (9-bit words if pe = 1) bits 3?: din b3?0 = xxxx, baud-rate divisor select bits (see table 6) d15 is present at dout on cs ? falling edge. consecutive bits are clocked out on sclk? falling edge.
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 17 www.maximintegrated.com table 3. read configuration (d15, d14 = 0, 1) notes: bit 15: dout r = 1, data is available to be read or is being read from the receive register or fifo. r = 0, receive register and fifo are empty. bit 14: dout t = 1, transmit buffer is empty. t = 0, transmit buffer is full. bit 13: dout fen = 0, fifo is enabled. fen = 1, fifo is disabled. bit 12: dout shdno = 1, software shutdown is enabled. shdno = 0, software shutdown is disabled. bit 11: dout tm = 1, transmit buffer empty interrupt is enabled. tm = 0, transmit buffer empty interrupt is disabled. bit 10: dout rm = 1, data available in the receive register or fifo interrupt is enabled. rm = 0, data available in the receive register or fifo interrupt is disabled. bit 9: dout pm = 1, parity bit high received interrupt is enabled. pm = 0, parity bit received interrupt is disabled. bit 8: dout ram = 1, receiver-activity (shutdown mode)/framing-error (normal operation) interrupt is enabled. ram = 0, receiver-activity (shutdown mode)/framing-error (normal operation) interrupt is disabled. bit 7: dout ir = 1, irda mode is enabled. ir = 0, irda mode is disabled. bit 6: dout st = 1, transmit two stop-bits. st = 0, transmit one stop-bit. bit 5: dout pe = 1, parity is enabled for both transmit (state of pt) and receive. pe = 0, parity is disabled for both transmit and receive. bit 4: dout l = 1, 7-bit words (8-bit words if pe = 1) l = 0, 8-bit words (9-bit words if pe = 1) bits 3?: dout b3?0 = xxxx baud-rate divisor select bits (see table 6) bit 15, 14: din 0,1 = read configuration bits 13?: din zeros bit 0: din if test = 1 and cs = 0, then rts =16xbaudclk test = 0, disables test mode d15 is present at dout on cs ? falling edge. consecutive bits are clocked out on sclk? falling edge. 14 1 t 6 0 st 7 0 ir 15 2 din 0 0 dout r b2 bit 3 0 b3 0 test b0 1 0 b1 4 0 l 5 0 pe 10 0 rm 11 0 tm 8 0 ram 9 0 pm 12 0 shdno 13 0 fen
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 18 www.maximintegrated.com table 4. write data (d15, d14 = 1, 0) d15 is present at dout on cs ? falling edge. consecutive bits are clocked out on sclk? falling edge. 14 0 t 6 d6t d6r 7 d7t d7r 15 2 din 1 d2t dout r d2r bit 3 d3t d3r 0 d0t d0r 1 d1t d1r 4 d4t d4r 5 d5t d5r 10 te ra/fe 11 0 0 8 pt pr 9 rts cts 12 0 0 13 0 0
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 19 www.maximintegrated.com table 5. read data (d15, d14 = 0, 0) notes: bits 15: dout r = 1, data is available to be read or is being read from the receive register or fifo. r = 0, receive register and fifo are empty. bit 14: dout t = 1, transmit buffer is empty. t = 0, transmit buffer is full. bits 13?1: dout zeros bit 10: dout ra/fe = receive-activity (uart shutdown)/framing-error (normal operation) bit bit 9: dout cts = cts input state. if cts = 0, then cts = 1 and vice versa. bit 8: dout pr = received parity bit. this is only valid if pe = 1. bits 7?: dout d7r?0r = received data bits. d7r = 0 for l = 1. bits 15, 14: din 0, 0 = read data bits 13?: din zeros d15 is present at dout on cs ? falling edge. consecutive bits are clocked out on sclk? falling edge. 0 0 13 0 0 12 cts 0 9 pr 0 8 0 0 11 ra/fe 0 10 d5r 0 5 d4r 0 4 d1r 0 1 d0r 0 0 d3r 0 3 bit d2r r dout 0 0 din 2 15 d7r 0 7 d6r 0 6 t 0 14
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 20 www.maximintegrated.com baud-rate generator the baud-rate generator determines the rate at which the transmitter and receiver operate. bits b3?0 in the write configuration register determine the baud-rate divisor (brd), which divides the x1 oscillator frequen- cy. the on-board oscillator operates with either a 1.8432mhz or a 3.6864mhz crystal or is driven at x1 with a 45% to 55% duty-cycle square wave. table 6 shows baud-rate divisors for given input codes as well as the baud rate for 1.8432mhz and 3.684mhz crystals. the generator? clock is 16-times the baud rate. interrupt sources and masks using the read data or write data register clears the interrupt irq, assuming the conditions that initiated the interrupt no longer exist. table 7 gives the details for each interrupt source. figure 6 shows the functional diagram for the interrupt sources and mask blocks. following are two examples of setting up an irq for the max3110e/max3111e: example 1. set up only the transmit buffer-empty inter- rupt. send the 16-bit word below into din of the max3110e/max3111e using the write configuration register. this 16-bit word configures the max3110e/ max3111e for 9600bps, 8-bit words, no parity, and one stop bit with a 1.8432mhz crystal. binary 1100100000001010 hex c80a example 2. set up only the data-available (or data- being-read) interrupt. send the 16-bit word below into din of the max3110e/max3111e using the write configuration register. this 16-bit word configures the max3110e/ max3111e for 9600bps, 8-bit words, no parity, and one stop bit with a 1.8432mhz crystal. binary 1100010000001010 hex c40a receive fifo the max3110e/max3111e contain an 8-word receive fifo for data received by the uart to minimize processor overhead. using the uart-software shut- down clears the receive fifo. upon power-up, the receive fifo is enabled. to disable the receive fifo, set the fen bit high when writing to the write configuration register. to check whether the fifo is enabled or disabled, read back the fen bit using the read configuration. uart software shutdown table 6. baud-rate selection* 115.2k 230.4k** baud rate (f osc = 3.6864mhz) baud b3 b2 b1 b0 2 0001 1 0000** division ratio 57.6k 115.2k** baud rate (f osc = 1.8432mhz) 28.8k 57.6k 8 0011 4 0010 14.4k 28.8k 7200 14.4k 1800 3600 128 0111 64 0110 900 1800 32 0101 16 0100 3600 7200 38.4k 76.8k 9600 19.2k 24 1011 12 1010 4800 9600 2400 4800 600 1200 384 1111 192 1110 300 600 96 1101 48 1100 1200 2400 6 1001 3 1000 19.2k 38.4k irq n rm mask tm mask pm mask transition on rx shutdown ram mask framing error shutdown ram mask r s q new data available data read transmit buffer empty data read pe = 1 and received parity bit = 1 pe = 0 or received parity bit = 0 r s q r s q figure 6. functional diagram for interrupt sources and mask blocks *standard baud rates shown in bold **default baud rate
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 21 www.maximintegrated.com when in software shutdown, the uart? oscillator turns off to reduce power dissipation. the uart enters shut- down by a software command (shdni bit = 1). the software shutdown is entered upon completing the transmission of the data in both the transmit register and the transmit-buffer register. the shdno bit is set when the uart enters shutdown. the microcontroller (?) monitors the shdno bit to determine when the uart is shut down and then shuts down the rs-232 transceivers. software shutdown clears the receive fifo, r, ra/fe, d0r?7r, pr, and pt registers and sets the t bit high. configuration bits ( rm , tm , pm , ram , ir, st, pe, l, b0?3, and rts) are programmable when shdno = 1 and cts is also readable. although ra is reset upon entering shutdown, it goes high when any transitions are detected on the rx pin. this allows the uart to monitor activity on the receiver when in shutdown. when taking the part out of software shutdown (shdni = 0), the oscillator turns on when cs goes high. after cs goes high, the oscillator typically takes about 25ms to stabilize. configure the uart after the oscillator has stabilized by using a write configuration that clears all registers but rts and cts. if a framing error occurs, you may have not waited long enough for the oscillator to stabilize. the hardware shutdown affects only the rs-232 trans- ceiver, and the software shutdown affects only the uart. see the rs-232 transceiver hardware shutdown section. dual charge-pump voltage converter the internal power supply consists of a regulated dual charge pump that provides output voltages of +5.5v (doubling charge pump) and -5.5v (inverting charge pump), using a +3.3v supply (max3111e) or a +5v sup- ply (max3110e). the charge pump operates in discontin- uous mode; if the output voltages are less than 5.5v, the charge pump is enabled, and if the output voltages exceed 5.5v, the charge pump is disabled. each charge pump includes internal flying capacitors and reservoir capacitors to generate the v+ and v- supplies. table 7. interrupt sources and masksbit descriptions meaning when set description received parity bit = 1 transition on rx when in shutdown; framing error when not in shutdown ra/fe ram this is the ra (rx-transition) bit in shutdown, and the framing-error (fe) bit in operating mode. ra is set if there has been a transition on rx since entering shutdown. ra is cleared when the max3110e/max3111e exits shutdown. irq is asserted when ra is set and ram = 1. fe is determined solely by the currently received data and is not stored in fifo. the fe bit is set if a zero is received when the first stop bit is expected. fe is cleared upon receipt of the next properly framed character. irq is asserted when fe is set and ram = 1. mask bit pr pm the pr bit reflects the value in the word currently in the receive-buffer register (oldest data available). the pr bit is set when parity is enabled (pe = 1) and the received parity bit is 1. the pr bit is cleared either when parity is not enabled (pe = 0) or when parity is enabled and the received bit is 0. an interrupt is issued based on the oldest pr value in the receiver fifo. the oldest pr value is the next value read by a read data operation. bit name data available r rm the r bit is set when new data is available to be read or when data is being read from the receive register/fifo. fifo is cleared when all data has been read. an interrupt is asserted as long as r = 1 and rm = 1. transmit buffer is empty t tm the t bit is set when the transmit buffer is ready to accept data. irq is asserted low if tm = 1 and the transmit buffer becomes empty. this source is cleared on the rising edge of sclk? 16th clock pulse when using a read data or write data operation. cs ? rising edge during a read data operation. although the interrupt is cleared, poll t to determine transmit-buffer status.
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 22 www.maximintegrated.com laplink is a trademark of traveling software. rs-232 transmitters the transmitters are inverting-level translators that con- vert cmos-logic levels to ?.0v eia/tia-232 levels. the transmitters guarantee a 230kbps data rate with worst-case loads of 3k in parallel with 1000pf, provid- ing compatibility with pc-to-pc communication soft- ware (such as laplink). transmitters can be paralleled because the outputs are forced into a high- impedance state when the device is in hardware shut- down ( shdn = gnd). the max3110e/max3111e permit the outputs to be driven up to ?2v while in shutdown. the transmitter inputs do not have pull-up resistors. connect unused inputs to gnd or v cc . rs-232 receivers the receivers convert rs-232 signals to cmos-logic output levels. the max3110e/max3111e receivers have inverting outputs and are always active, even when the part is in hardware (or software) shutdown. rs-232 transceiver hardware shutdown supply current falls to i ccshdn(h) when in hardware shutdown mode ( shdn = low). when shut down, the device? charge pumps are turned off, v+ is pulled down to v cc , v- is pulled to ground, and the transmitter outputs are disabled (high impedance). the time required to exit shutdown is typically 100?, as shown in figure 7. connect shdn to v cc if the shutdown mode is not used. the uart software shutdown does not affect the rs-232 transceiver. 15kv esd protection as with all maxim devices, esd-protection structures are incorporated on all pins to protect against electro- static discharges encountered during handling and assembly. the driver outputs and receiver inputs of the max3110e/max3111e have extra protection against static electricity. maxim? engineers have developed state-of-the-art structures to protect these pins against esd of ?5kv without damage. the esd structures withstand high esd in all states: normal operation, shut- down, and powered down. after an esd event, the max3110e/max3111e keep working without latchup, whereas competing rs-232 products can latch and must be powered down to remove latchup. esd protection is tested in various ways; the transmitter outputs and receiver inputs devices are characterized for protection to the following limits: ?5kv using the human body model 8kv using the contact-discharge method specified in iec 1000-4-2 ?5kv using the air-gap method specified in iec 1000-4-2 esd test conditions esd performance depends on a variety of conditions. contact maxim? quality assurance (qa) group for a reliability report that documents test setup, methodolo- gy, and results. human body model figure 8a shows the human body model, and figure 8b shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of inter- est, which is then discharged into the test device through a 1.5k resistor. iec 1000-4-2 the iec 1000-4-2 standard covers esd testing and performance of finished equipment; it does not specifi- cally refer to integrated circuits. the max3110e/ max3111e help you design equipment that meets level 4 (the highest level) of iec 1000-4-2 without the need for additional esd-protection components. the major difference between tests done using the human body model and iec 1000-4-2 is higher peak current in iec 1000-4-2, because series resistance is lower in the iec 1000-4-2 model. hence, the esd that withstands voltage measured to iec 1000-4-2 is gener- ally lower than that measured using the human body model. figure 9a shows the iec 1000-4-2 model, and figure 9b shows the current waveform for the ?kv iec 1000-4-2 level 4 esd contact-discharge test. 40 s/div shdn t2out t1out 5v/div 0 2v/div 0 v cc = 3.3v figure 7. max3111e transmitter outputs exiting shutdown or powering up
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 23 www.maximintegrated.com the air-gap test involves approaching the device with a charged probe. the contact-discharge method connects the probe to the device before the probe is energized. machine model the machine model for esd tests all pins using a 200pf storage capacitor and zero discharge resis- tance. its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. of course, all pins require this protec- tion during manufacturing, not just rs-232 inputs and outputs. therefore, after pc board assembly, the machine model is less relevant to i/o ports. applications information crystals, oscillators, and ceramic resonators the max3110e/max3111e include an oscillator circuit derived from an external crystal oscillator for baud- rate generation. for standard baud rates, use a 1.8432mhz or 3.6864mhz crystal. the 1.8432mhz crystal results in lower operating current; however, the 3.6864mhz crystal may be more readily available in surface mount. charge-current limit resistor discharge resistance storage capacitor c s 100pf r c 1m r d 1500 high- voltage dc source device under test figure 8a. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 8b. human body model current waveform charge-current limit resistor discharge resistance storage capacitor c s 150pf r c 50m to 100m r d 330 high- voltage dc source device under test t r = 0.7ns to 1ns 30ns 60ns t 100% 90% 10% i peak i figure 9a. iec 1000-4-2 esd test model figure 9b. iec 1000-4-2 esd generator current waveform
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 24 www.maximintegrated.com ceramic resonators are low-cost alternatives to crystals and operate similarly, although the q and accuracy are lower. some ceramic resonators are available with inte- gral load capacitors, which can further reduce cost. the tradeoff between crystals and ceramic resonators is in initial-frequency accuracy and temperature drift. keep the total error in the baud-rate generator below 1% for reliable operation with other systems. this is accom- plished easily with a crystal and, in most cases, is achieved with ceramic resonators. table 8 lists different types of crystals and resonators and their suppliers. th e max3110e/max3111e? oscillator supports paral- lel-resonant mode crystals and ceramic resonators or can be driven from an external clock source. internally, the oscillator consists of an inverting amplifier with its input, x1, tied to its output, x2, by a bias network that self-biases the inverter at approximately v cc /2. the external feedback circuit, usually a crystal from x2 to x1, provides 180 of phase shift, causing the circuit to oscil- late. as shown in the standard application circuit, the crystal or resonator is connected between x1 and x2, with the load capacitance for the crystal being the series combination of c1 and c2. for example, for a 1.8432mhz crystal with a specified load capacitance of 11pf, use capacitors of 22pf on either side of the crystal to ground. series-resonant mode crystals have a slight frequency error, typically oscillating 0.03% higher than specified series-resonant frequency when operated in parallel mode. note: it is very important to keep crystal, resonator, and load-capacitor leads and traces as short and direct as possible. make the x1 and x2 trace lengths and ground tracks short, with no intervening traces. this helps minimize parasitic capacitance and noise pickup in the oscillator, and reduces emi. minimize capacitive loading on x2 to minimize supply current. the max3110e/max3111e? x1 input can be driven directly by an external cmos clock source. the trip level is approximately equal to v cc /2. make no connec- tion to x2 in this mode. if a ttl or non-cmos clock source is used, ac-couple it with a 10nf capacitor to x1. a 2v peak-to-peak swing on the input is required for reliable operation. rs-232 transmitter outputs exiting shutdown figure 7 shows two rs-232 transmitter outputs exiting shutdown mode. as they become active, the two trans- mitter outputs are shown going to opposite rs-232 lev- els (one transmitter input is high; the other is low). each transmitter is loaded with 3k in parallel with 2500pf. the transmitter outputs display no ringing or undesir- able transients as they come out of shutdown. note that the transmitters are enabled only when the magnitude of v- exceeds approximately 3v. table 8. component and supplier list murata north america ecs international, inc. supplier csa1.84mg ecs-18-13-1 part number 800-831-9172 913-782-7787 phone number description 1.8432 through-hole ceramic resonator 1.8432 through-hole crystal (hc-49/u) frequency (mhz) 47 25 typical c1, c2 (pf) ecs international, inc. ecs international, inc. ecs-36-20-5p ecs-36-18-4 913-782-7787 913-782-7787 3.6864 smt crystal 3.6864 through-hole crystal (hc-49/us) 39 33 avx/kyocera pbrc-3.68b 803-448-9411 3.6864 smt ceramic resonator none (integral)
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 25 www.maximintegrated.com high data rates the max3110e/max3111e maintain the rs-232 ?.0v minimum transmitter output-voltage specification even at the highest guaranteed data rate. figure 10 shows a transmitter loopback test circuit. figure 11 shows a loopback test result at 120kbps, and figure 12 shows the same test at 250kbps. for figure 11, both transmit- ters are driven simultaneously at 120kbps into an rs- 232 receiver in parallel with 1000pf. for figure 12, a single transmitter is driven at 250kbps, and both trans- mitters are loaded with an rs-232 receiver in parallel with 1000pf. interconnection with 3.3v and 5v logic the max3110e/max3111e can directly interface with various 3.3v and 5v logic families, including act and hct cmos. see table 9 for more information on possi- ble combinations of interconnections. typical applications the max3110e/max3111e each contain a uart, two rs-232 drivers, and two rs-232 receivers in one pack- age. the standard rs-232 typical operating circuit is shown in figure 13. 2 s/div t1in t1out r1out 5v/div 5v/div 5v/div v cc = 3.3v (max3111e), v cc = 5.0v (max3110e) figure 11. loopback test result at 120kbps max3110e max3111e 5k r_ in r_ out c2- c2+ c1- c1+ v- v+ v cc 0.1 f v cc shdn t_ out t_ in gnd v cc 1000pf figure 10. loopback test circuit 2 s/div t1in t1out r1out 5v/div 5v/div 5v/div v cc = 3.3v (max3111e), v cc = 5.0v (max3110e) figure 12. loopback test result at 250kbps rx tx v cc v cc shdn 232 active 232 shutdown din dout sclk cs irq 100k p rs-232 i/o c2+ gnd c2- v+ v- c1+ c1- max3110e max3111e cts r2out r1out t1in t2in t1out x2 x1 rts r1in r2in t2out figure 13. rs-232 typical operating circuit
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 26 www.maximintegrated.com an ir and rs-232 typical operating circuit is shown in figure 14. since the max3110e/max3111e? internal uart has irda capability, a standard ir transceiver (the max3120) can be used to provide the irda com- munication. the two-driver/two-receiver rs-232 trans- ceiver can be used with a software uart to provide rs-232 communication. 9-bit networks the max3110e/max3111e support a common multi- drop communication technique referred to as 9-bit mode. in this mode, the parity bit is set to indicate a message that contains a header with a destination address. the max3110e/max3111e? parity mask can be set to generate interrupts for this condition. operating a network in this mode reduces the process- ing overhead of all nodes by enabling the slave con- trollers to ignore most message traffic. this relieves the remote processor to handle more useful tasks. table 9. logic-family compatibility with various supply voltages cts rx tx v cc shdn 232 active 232 shutdown din dout sclk cs c1+ c1- v+ v- tx rx txd rxd irda i/o p rs-232 i/o uart in irda mode non-irda uart c2+ gnd c2- max3110e max3111e max3120 rts r2out r1out t1in t2in r2in r1in t1out x2 x1 t2out irq 100k v cc figure 14. ir and rs-232 typical operating circuit 5 (max3111e) logic power-supply voltage (v) 3.3 (max3111e) 5 (max3110e) compatible with act and hct cmos, and with ac, hc, or cd4000 cmos compatibility compatible with all cmos families compatible with all ttl and cmos fami- lies 3.3 v cc supply voltage (v) 3.3 5
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 27 www.maximintegrated.com in 9-bit mode, the max3110e/max3111e is set up with eight bits plus parity. the parity bit in all normal mes- sages is clear but is set in an address-type message. the max3110e/max3111e? parity-interrupt mask gen- erates an interrupt on high parity when enabled. when the master sends an address message with the parity bit set, all max3110e/max3111e nodes issue an inter- rupt. all nodes then retrieve the received byte to com- pare to their assigned address. once addressed, the node continues to process each received byte. if the node was not addressed, it ignores all message traffic until a new address is sent out by the master. the parity/9th-bit interrupt is controlled only by the data in the receive register and is not affected by data in the fifo, so the most effective use of the parity/9th-bit interrupt is with fifo disabled. with the fifo disabled, received non-address words can be ignored and not even read from the uart. for more detailed informa- tion on 9-bit mode, refer to the max3100 data sheet. sir irda mode the max3110e/max3111e? irda mode can be used to communicate with other irda sir-compatible devices or to reduce power consumption in opto-isolat- ed applications. in irda mode, a bit period is shortened to 3/16 of a baud period (1.61? at 115,200 baud). a data zero is transmitted as a pulse of light (tx pin = logic low, rx pin = logic high), as shown in figure 15. in receive mode, the rx signal? sampling is done halfway into the transmission of a high level. the sam- pling is done once (instead of three times, as in normal mode). the max3110e/max3111e ignore pulses short- er than approximately 1/16 of the baud period. the irda device that is communicating with the max3110e/ max3111e must be set to transmit pulses at 3/16 of the baud period. for compatibility with other irda devices, set the format to 8-bit data, one stop, no parity. for more detailed information on sir irda mode, refer to the max3100 data sheet. layout and power-supply considerations the max3110e/max3111e require basic layout tech- niques and fundamental power supply considerations. the minimum requirements include: (1) placing a 1? ceramic bypass capacitor as close as possible to v cc , preferably right next to the v cc lead or on the opposite side of the pcb directly below the v cc lead; (2) using an internal ground plane within the pcb, returning all circuit grounds to this ground plane, or using a ?tar ground technique where all circuit grounds are returned to a common ground point at the ?nd?lead of the ic; (3) ensuring that the power source to the ic has a low inductive path and is high-frequency bypassed to absorb esd events with significant changes in the supply voltage. start stop start stop normal rx uart frame data bits 01 1 11 1 000 0 normal uart tx 11 11 1 000 0 irda rx irda tx figure 15. irda timing
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 28 www.maximintegrated.com this is a c-language outline of an interrupt-driven software driver that interfaces to a max3110e/max3111e, providing an intermediate layer between the bit-manipulation subroutine and the familiar putchar / getchar subroutines. user must supply code for managing the transmit and receive queues, as well as the low-level hardware interface itself. the interrupt control hardware must be initialized before this driver is called. char is an 8 bit character. int is a 16 bit unsigned integer. & is the bitwise boolean and operator. | is the bitwise boolean or operator. /* high level interface routine to put a character to the max3110e/max3111e. */ putchar ( char c ) { enqueue ( txqueue, c ); /* enable the transmit-buffer-empty interrupt */ config = config | 0x0800; /* set the tm bit */ config = config | 0xc000; /* set bits 15 and 14 */ max3110e/max3111e ( config ); } /* high level interface routine to get a character from the max3110e/max3111e. ** wait for a character to be received, if necessary. */ char getchar ( ) { while ( isqueueempty ( rxqueue ) ) /* wait for data to be received */ ; return dequeue ( rxqueue ); } /* configure the max3110e/max3111e with the specified baud rate. */ configuremax3110e/max3111e ( int baud_rate_index ) { baud_rate_index = baud_rate_index & 0x000f; /* restrict to a 4 bit field */ config = 0xc400 + baud_rate_index; /* enable received data interrupt */ max3110e/max3111e ( config ); } /* private variable that stores the configuration settings for the max3110e/max3111e */ int config; /* low level communication routine between the computer and the max3110e/max3111e. ** this is a private routine to be used only within the driver software. */ int max3110e/max3111e ( int mosi ) { int miso; /* this is interface-specific. ** transmit 16 bits of master-out, slave-in data, msb first, ** while simultaneously receiving 16 bits of master-in, slave-out data. ** if and spi hardware interface is available, use (cpol=0,cpha=0) mode. ** lacking specialized hardware, just set and clear i/o bits to generate ** the waveform in figures 2 and 3 in the max3110e/max311e data sheet. */ return miso; /* return 16 bits of master-in, slave-out data, msb first */ } listing 1. outline for a max3110e/max3111e software driver
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 29 www.maximintegrated.com /* this driver needs a txqueue transmit-data queue and a rxqueue receive-data queue. ** these can be ring buffers or any other kind of first-in, first-out data queue. */ enqueue ( queue , char ) char dequeue ( queue ) true/false isqueueempty ( queue ) /* interrupt service routine called when the max3110emax3111e's int pin falls to a low level. ** this is a private routine to be used only within the driver software. */ servicemax3110e/max3111eint ( ) { int rxdata; int txdata; char c; /* issue a read data command to discover the cause of the interrupt */ rxdata = max3110e/max3111e ( 0 ); if ( rxdata & 0x8000 ) /* the r bit = 1 */ { c = rxdata & 0x00ff; /* get the received character data */ enqueue ( rxqueue, c ); } if ( rxdata & 0x4000 ) /* the t bit = 1 */ { if ( isqueueempty ( txqueue ) ) { /* mask the transmit-buffer-empty interrupt */ config = config & ~ 0x0800; /* clear the tm bit */ config = config | 0xc000; /* set bits 15 and 14 */ max3110e/max3111e ( config ); } else /* transmit some data */ { /* issue a write data command */ txdata = dequeue ( txqueue ); c = txdata & 0x00ff; /* get the transmit character */ max3110e/max3111e ( 0x8000 | c ); } } } /* end of servicemax3110e/max3111eint */ listing 1. outline for a max3110e/max3111e software driver (continued)
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated | 30 www.maximintegrated.com 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 t2out gnd v- c2- c2+ c1- din c1+ v+ shdn irq cs sclk dout tx rx rts cts x1 x2 v cc t1out r1in r1out t1in t2in r2out r2in narrow dip/wide so top view max3110e max3111e pin configuration ordering information (continued) 3.3 3.3 3.3 3.3 5 v cc (v) 5 28 plastic dip -40? to +85? max3110eeni 28 wide so -40? to +85? max3110eewi 28 plastic dip 28 wide so -40? to +85? -40? to +85? max3111eeni max3111eewi 28 plastic dip 28 wide so 0? to +70? 0? to +70? max3111ecni max3111e cwi pin- package temp. range part package type package code document no. 28 wide so 21-0042 28 plastic dip 21-0043 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per tains to the package regardless of rohs status.
max3110e/max3111e spi/microwire-compatible uart and 15kv esd-protected rs-232 transceivers with internal capacitors maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integr ated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time . the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. 2015 maxim integrated products , inc. | 31 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds web site at www.maximintegrated.com. revision history revision number revision date description pages changed 0 7/99 initial release. 1 12/05 added the soldering temperature to the absolute maximum ratings 2 2 2/15 updated the benefits and features section 1

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